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300 MHz, 32 x 32 Buffered Analog Crosspoint Switch ADV3200/ADV3201
FEATURES
Large, 32 x 32, nonblocking switch array G = +1 (ADV3200) or G = +2 (ADV3201) operation Pin-compatible 32 x 16 versions available (ADV3202/ADV3203) Single 5 V supply, dual 2.5 V supply, or dual 3.3 V supply (G = +2) Serial programming of switch array 2:1 OSD insertion mux per output Input sync-tip clamp High impedance output disable allows connection of multiple devices with minimal output bus load Excellent video performance 60 MHz, 0.1 dB gain flatness 0.1% differential gain error (RL = 150 ) 0.1 differential phase error (RL = 150 ) Excellent ac performance Bandwidth: >300 MHz Slew rate: >400 V/s Low power: 1.25 W Low all hostile crosstalk of -48 dB @ 5 MHz Reset pin allows disabling of all outputs Connected through a capacitor to ground, provides power-on reset capability 176-lead exposed pad LQFP (24 mm x 24 mm)
CLK 193-BIT SHIFT REGISTER DATA IN UPDATE CS RESET ENABLE/ BYPASS SYNC-TIP CLAMP 193 PARALLEL LATCH 192 32 x 5:32 DECODERS DATA OUT
FUNCTIONAL BLOCK DIAGRAM
VPOS VNEG DVCC DGND
ADV3200 (ADV3201)
32 ENABLE/ DISABLE
1024
OUTPUT BUFFER G = +1 (G = +2)
32 INPUTS
. . .
. . .
SWITCH MATRIX
OSD MUX
. . .
. . .
32 OUTPUTS
32 REFERENCE
32
VCLAMP
OSD OSD VREF INPUTS SWITCHES
APPLICATIONS
CCTV surveillance Routing of high speed signals including Composite video (NTSC, PAL, S, SECAM) RGB and component video routing Compressed video (MPEG, Wavelet) Video conferencing
Figure 1.
GENERAL DESCRIPTION
The ADV3200/ADV3201 are 32 x 32 analog crosspoint switch matrices. They feature a selectable sync-tip clamp input for ac-coupled applications and an on-screen display (OSD) insertion mux. With -48 dB of crosstalk and -80 dB isolation at 5 MHz, the ADV3200/ADV3201 are useful in many high density routing applications. The 0.1 dB flatness out to 60 MHz makes the ADV3200/ADV3201 ideal for composite video switching. The 32 independent output buffers of the ADV3200/ADV3201 can be placed into a high impedance state for paralleling crosspoint outputs so that off channels present minimal loading to an output bus if building a larger array. The part is available in a gain of +1 (ADV3200) or +2 (ADV3201) for ease of use in back-terminated load applications. A single 5 V supply, dual 2.5 V supplies, or dual 3.3 V supplies (G = +2) can be used while consuming only 250 mA of idle current with all outputs enabled. The channel switching is performed via a double buffered, serial digital control, which can accommodate daisy chaining of several devices. The ADV3200/ADV3201 are packaged in a 176-lead exposed pad LQFP (24 mm x 24 mm) and are available over the extended industrial temperature range of -40C to +85C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07176-001
ADV3200/ADV3201 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 OSD Disabled ................................................................................ 3 OSD Enabled ................................................................................. 4 Timing Characteristics (Serial Mode) ....................................... 5 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 Power Dissipation ......................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Truth Table and Logic Diagram ............................................... 11 I/O Schematics ................................................................................ 12 Typical Performance Characteristics ........................................... 13 ADV3200 ..................................................................................... 13 ADV3201 ..................................................................................... 20 Theory of Operation ...................................................................... 27 Applications Information .............................................................. 29 Programming .............................................................................. 29 AC Coupling of Inputs .............................................................. 29 On-Screen Display (OSD) ......................................................... 31 Decoupling .................................................................................. 31 Power Dissipation....................................................................... 31 Crosstalk ...................................................................................... 32 PCB Termination Layout........................................................... 34 Outline Dimensions ....................................................................... 36 Ordering Guide .......................................................................... 36
REVISION HISTORY
10/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADV3200/ADV3201 SPECIFICATIONS
OSD DISABLED
VS = 2.5 V (ADV3200), VS = 3.3 V (ADV3201) at TA = 25C, G = +1 (ADV3200), G = +2 (ADV3201), RL = 150 , all configurations, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Gain Flatness Settling Time Slew Rate NOISE/DISTORTION PERFORMANCE Differential Gain Error ADV3200 ADV3201 Differential Phase Error ADV3200 ADV3201 Crosstalk, All Hostile, RTI Test Conditions/Comments 200 mV p-p 2 V p-p 0.1 dB, 200 mV p-p 0.1 dB, 2 V p-p 1%, 2 V step 2 V step, peak NTSC or PAL 0.06 0.1 NTSC or PAL 0.06 0.03 -48 -65 -23 -30 -80 25 22 Degrees Degrees dB dB dB dB dB nV/Hz nV/Hz % % Min Typ 300 120 60 40 6 400 Max Unit MHz MHz MHz MHz ns V/s
Off Isolation, Input-to-Output, RTI Input Voltage Noise ADV3200 ADV3201 DC PERFORMANCE Gain Error ADV3200 ADV3201 Gain Matching OUTPUT CHARACTERISTICS Output Impedance ADV3200 ADV3201 Output Capacitance Output Voltage Range ADV3200 ADV3201 INPUT CHARACTERISTICS Input Offset Voltage Input Voltage Range ADV3200 ADV3201
f = 5 MHz, RL = 150 f = 5 MHz, RL = 1 k f = 100 MHz, RL = 150 f = 100 MHz, RL = 1 k f = 5 MHz, one channel 0.1 MHz to 50 MHz
No load (broadcast mode) Broadcast mode No load (broadcast mode) Broadcast mode No load, channel-to-channel Channel-to-channel DC, enabled DC, disabled DC, disabled Disabled
0.5 0.5 0.5 0.5 0.5 0.8 0.15 1000 4 3.7 -1.2 to +1.2 -1.6 to +2.0 -2.0 to +2.0 5 -1.1 to +1.1 -0.75 to +0.75 -0.75 to +0.75 -1.2 to +1.2 -0.8 to +1.0 -1.0 to +1.0
1.75 2.2 2.2 2.7 2.8 3.4
% % % % % % k k pF V V V
900 3.2
No output load
-1.1 to +1.1 -1.5 to +1.5 -1.5 to +1.5
30
mV V V V
No output load
Rev. 0 | Page 3 of 36
ADV3200/ADV3201
Parameter Input Capacitance Input Resistance Input Bias Current Test Conditions/Comments Min 1 0.1 -2.9 -10 Typ 3 4 3 -1 -3 50 40 300 Max Unit pF M A mA A ns ns mV p-p
Sync-tip clamp enabled, VIN = VCLAMP + 0.1 V Sync-tip clamp enabled, VIN = VCLAMP - 0.1 V Sync-tip clamp disabled 50% update to 1% settling 50% update to 1% settling IN00 to IN31, RTI
12 -0.25
SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) POWER SUPPLIES Supply Current ADV3200 ADV3201 DVCC Supply Voltage Range PSR ADV3200 ADV3201 OPERATING TEMPERATURE RANGE Temperature Range JA
VPOS or VNEG, outputs enabled, no load VPOS or VNEG, outputs disabled VPOS or VNEG, outputs enabled, no load VPOS or VNEG, outputs disabled VPOS - VNEG VNEG, VPOS, f = 1 MHz
250 120 260 130 2.5 5 10% to 6.6 10% -50 -45
300 155 310 165 3.5
mA mA mA mA mA V
dB dB C C/W
Operating (still air) Operating (still air)
-40 to +85 16
OSD ENABLED
VS = 2.5 V (ADV3200), VS = 3.3 V (ADV3201) at TA = 25C, G = +1 (ADV3200), G = +2 (ADV3201), RL = 150 , all configurations, unless otherwise noted. Table 2.
Parameter OSD DYNAMIC PERFORMANCE -3 dB Bandwidth ADV3200 ADV3201 Gain Flatness Settling Time Slew Rate OSD NOISE/DISTORTION PERFORMANCE Differential Gain Error ADV3200 ADV3201 Differential Phase Error ADV3200 ADV3201 Input Voltage Noise ADV3200 ADV3201 Test Conditions/Comments Min Typ Max Unit
200 mV p-p 2 V p-p 200 mV p-p 2 V p-p 0.1 dB, 200 mV p-p 0.1 dB, 2 V p-p 1%, 2 V step 2 V step, peak NTSC or PAL
170 135 150 130 35 35 6 400
MHz MHz MHz MHz MHz MHz ns V/s
0.12 0.35 NTSC or PAL 0.06 0.04 0.5 MHz to 50 MHz 27 25
Rev. 0 | Page 4 of 36
% % Degrees Degrees nV/Hz nV/Hz
ADV3200/ADV3201
Parameter OSD DC PERFORMANCE Gain Error ADV3200 ADV3201 OSD INPUT CHARACTERISTICS Input Offset Voltage Input Bias Current OSD SWITCHING CHARACTERISTICS OSD Switch Delay, 2 V Step OSD Switching Transient (Glitch) ADV3200 ADV3201 Test Conditions/Comments Min Typ Max Unit
No load No load
0.1 0.1 0.1 0.1 5 -4 20 15 40
2.3 2.7 2.2 2.7 30
% % % % mV A ns mV p-p mV p-p
-10 50% OSD switch to 1% settling
TIMING CHARACTERISTICS (SERIAL MODE)
Table 3.
Parameter Serial Data Setup Time CLK Pulse Width Serial Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulse Width CLK to DATA OUT Valid Propagation Delay, UPDATE to Switch On or Off Data Load Time, CLK = 5 MHz, Serial Mode RESET Time Symbol t1 t2 t3 t4 t5 t6 t7 Min 40 50 50 150 40 130 50 38.6 160 Limit Typ Max Unit ns ns ns ns ns ns ns ns s ns
50
160
1 CS 0 1 CLK 0
t2
t4
LOAD DATA INTO SERIAL REGISTER ON RISING EDGE
t1
1 DATA IN 0 1 = LATCHED UPDATE 0 = TRANSPARENT
t3
OUT31 (D5) OUT00 (D0)
CLAMP ON/OFF
t5
TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL
t6
t7
DATA OUT
07176-002
Figure 2. Timing Diagram, Serial Mode
Rev. 0 | Page 5 of 36
ADV3200/ADV3201
0 1 2 3 4 5 6 7 8 9 10 11 12 13 19 25 31 36 187 192
CLK
DATA IN
CONNECT TO IN00 CONNECT TO IN01 CONNECT TO IN31 CONNECT TO IN07 ENABLE SYNC-TIP CLAMP ENABLE OUT31 DISABLE OUT29 ENABLE OUT30 ENABLE OUT28 ENABLE OUT27 ENABLE OUT00 CONNECT TO IN00 DON'T CARE
UPDATE
T=0
INCREASING TIME
Figure 3. Programming Example
Table 4. Logic Levels, DVCC = 3.3 V
VIH RESET, CS, CLK, DATA IN, UPDATE, OSDS 2.5 V min VIL RESET, CS, CLK, DATA IN, UPDATE, OSDS 0.8 V max VOH DATA OUT VOL DATA OUT IIH RESET, CS, CLK, DATA IN, UPDATE, OSDS 0.5 A typ IIL RESET, CS, CLK, DATA IN, UPDATE, OSDS -0.5 A typ IOH DATA OUT IOL DATA OUT
2.7 V min
0.5 V max
3 mA typ
07176-105
-3 mA typ
Rev. 0 | Page 6 of 36
ADV3200/ADV3201 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Analog Supply Voltage (VPOS - VNEG) Digital Supply Voltage (DVCC - DGND) Ground Potential Difference (VNEG - DGND) Maximum Potential Difference DVCC - VNEG Disabled Outputs ADV3200 (|VOSD - VOUT|) ADV3201 (|VOSD - (VOUT + VREF)/2|) |VCLAMP - VINxx| VREF Input Voltage ADV3200 ADV3201 Analog Input Voltage Digital Input Voltage Output Voltage (Disabled Analog Output) Output Short-Circuit Duration Output Short-Circuit Current Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 7.5 V 6V +0.5 V to -4 V
POWER DISSIPATION
The ADV3200/ADV3201 are operated with 2.5 V, 5 V, or 3.3 V supplies and can drive loads down to 150 , resulting in a large range of possible power dissipations. For this reason, extra care must be taken to derate the operating conditions based on ambient temperature. The ADV3200/ADV3201 are packaged in a 176-lead exposed pad LQFP. The junction-to-ambient thermal impedance (JA) of the ADV3200/ADV3201 is 16C/W. For long-term reliability, the maximum allowed junction temperature of the die should not exceed 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. Figure 4 shows the range of allowed internal die power dissipations that meet these conditions over the -40C to +85C ambient temperature range. When using Figure 4, do not include external load power in the maximum power calculation, but do include load current dropped on the die output transistors.
9 TJ = 150C 8
MAXIMUM POWER (W)
9.4 V <3 V <3 V 6V VPOS - 3.5 V to VNEG + 3.5 V VPOS - 4 V to VNEG + 4 V VNEG to VPOS DVCC (VPOS - 1 V) to (VNEG + 1 V) Momentary 45 mA -65C to +125C -40C to +85C 300C 150C
7
6
25
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance
Package Type 176-Lead LQFP_EP JA 16 Unit C/W
35 45 55 65 AMBIENT TEMPERATURE (C)
75
85
Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. 0 | Page 7 of 36
07176-003
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
5
4
3 15
ADV3200/ADV3201 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DGND OSD01 OSD02 OSD03 OSD04 OSD05 OSD06 OSD07 VPOS OUT00 VNEG OUT01 VPOS OUT02 VNEG OUT03 VPOS OUT04 VNEG OUT05 VPOS OUT06 VNEG OUT07 VPOS OUT08 VNEG OUT09 VPOS OUT10 VNEG OUT11 VPOS OUT12 VNEG OUT13 VPOS OUT14 VNEG OUT15 VPOS OSD08 OSD09 OSD10
173 168 158 157 156 155 153 152 151 150 175 174 172 171 170 167 166 165 164 163 162 161 160 159 148 176 169 144 143 142 141 140 137 154 149 147 145 138 134 146 139 136
DVCC OSD00 RESET CLK DATA IN DATA OUT UPDATE CS OSDS15 IN00 OSDS14 IN01 OSDS13 IN02 OSDS12 IN03 OSDS11 IN04 OSDS10 IN05 OSDS09 IN06 OSDS08 IN07 OSDS07 IN08 OSDS06 IN09 OSDS05 IN10 OSDS04 IN11 OSDS03 IN12 OSDS02 IN13 OSDS01 IN14 OSDS00 IN15 VNEG VREF VCLAMP OSD31
135
133
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 PIN 1
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113
ADV3200/ADV3201
TOP VIEW (Not to Scale)
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
VNEG OSD11 OSD12 OSD13 OSD14 OSD15 OSDS16 IN16 OSDS17 IN17 OSDS18 IN18 OSDS19 IN19 OSDS20 IN20 OSDS21 IN21 OSDS22 IN22 OSDS23 IN23 OSDS24 IN24 OSDS25 IN25 OSDS26 IN26 OSDS27 IN27 OSDS28 IN28 OSDS29 IN29 OSDS30 IN30 OSDS31 IN31 VPOS OSD16 OSD17 OSD18 OSD19 VNEG
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
NOTES 1. OSDSxx: OSD SELECT FOR OUTxx OSDxx: OSD VIDEO INPUT FOR OUTxx 2. THE EXPOSED PAD SHOULD BE CONNECTED TO ANALOG GROUND.
OSD30 OSD29 OSD28 OSD27 OSD26 OSD25 OSD24 VPOS OUT31 VNEG OUT30 VPOS OUT29 VNEG OUT28 VPOS OUT27 VNEG OUT26 VPOS OUT25 VNEG OUT24 VPOS OUT23 VNEG OUT22 VPOS OUT21 VNEG OUT20 VPOS OUT19 VNEG OUT18 VPOS OUT17 VNEG OUT16 VPOS OSD23 OSD22 OSD21 OSD20
88
Figure 5. Pin Configuration
Rev. 0 | Page 8 of 36
07176-004
ADV3200/ADV3201
Table 7. Pin Function Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Mnemonic DVCC OSD00 RESET CLK DATA IN DATA OUT UPDATE CS OSDS15 IN00 OSDS14 IN01 OSDS13 IN02 OSDS12 IN03 OSDS11 IN04 OSDS10 IN05 OSDS09 IN06 OSDS08 IN07 OSDS07 IN08 OSDS06 IN09 OSDS05 IN10 OSDS04 IN11 OSDS03 IN12 OSDS02 IN13 OSDS01 IN14 OSDS00 IN15 VNEG VREF VCLAMP OSD31 OSD30 OSD29 OSD28 OSD27 OSD26 Description Digital Positive Power Supply. OSD Input Number 0. Control Pin: First and Second Rank Reset. Control Pin: Serial Data Clock. Control Pin: Serial Data In. Control Pin: Serial Data Out. Control Pin: Second Rank Write Strobe. Control Pin: Chip Select. Control Pin: OSD Select Number 15. Input Number 0. Control Pin: OSD Select Number 14. Input Number 1. Control Pin: OSD Select Number 13. Input Number 2. Control Pin: OSD Select Number 12. Input Number 3. Control Pin: OSD Select Number 11. Input Number 4. Control Pin: OSD Select Number 10. Input Number 5. Control Pin: OSD Select Number 9. Input Number 6. Control Pin: OSD Select Number 8. Input Number 7. Control Pin: OSD Select Number 7. Input Number 8. Control Pin: OSD Select Number 6. Input Number 9. Control Pin: OSD Select Number 5. Input Number 10. Control Pin: OSD Select Number 4. Input Number 11. Control Pin: OSD Select Number 3. Input Number 12. Control Pin: OSD Select Number 2. Input Number 13. Control Pin: OSD Select Number 1. Input Number 14. Control Pin: OSD Select Number 0. Input Number 15. Analog Negative Power Supply. Reference Voltage. See the Theory of Operation section for details. Sync-Tip Clamp Voltage. See the Theory of Operation section for details. OSD Input Number 31. OSD Input Number 30. OSD Input Number 29. OSD Input Number 28. OSD Input Number 27. OSD Input Number 26. Pin 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Mnemonic OSD25 OSD24 VPOS OUT31 VNEG OUT30 VPOS OUT29 VNEG OUT28 VPOS OUT27 VNEG OUT26 VPOS OUT25 VNEG OUT24 VPOS OUT23 VNEG OUT22 VPOS OUT21 VNEG OUT20 VPOS OUT19 VNEG OUT18 VPOS OUT17 VNEG OUT16 VPOS OSD23 OSD22 OSD21 OSD20 VNEG OSD19 OSD18 OSD17 OSD16 VPOS IN31 OSDS31 IN30 OSDS30 IN29 OSDS29 Description OSD Input Number 25. OSD Input Number 24. Analog Positive Power Supply. Output Number 31. Analog Negative Power Supply. Output Number 30. Analog Positive Power Supply. Output Number 29. Analog Negative Power Supply. Output Number 28. Analog Positive Power Supply. Output Number 27. Analog Negative Power Supply. Output Number 26. Analog Positive Power Supply. Output Number 25. Analog Negative Power Supply. Output Number 24. Analog Positive Power Supply. Output Number 23. Analog Negative Power Supply. Output Number 22. Analog Positive Power Supply. Output Number 21. Analog Negative Power Supply. Output Number 20. Analog Positive Power Supply. Output Number 19. Analog Negative Power Supply. Output Number 18. Analog Positive Power Supply. Output Number 17. Analog Negative Power Supply. Output Number 16. Analog Positive Power Supply. OSD Input Number 23. OSD Input Number 22. OSD Input Number 21. OSD Input Number 20. Analog Negative Power Supply. OSD Input Number 19. OSD Input Number 18. OSD Input Number 17. OSD Input Number 16. Analog Positive Power Supply. Input Number 31. Control Pin: OSD Select Number 31. Input Number 30. Control Pin: OSD Select Number 30. Input Number 29. Control Pin: OSD Select Number 29.
Rev. 0 | Page 9 of 36
ADV3200/ADV3201
Pin 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 Mnemonic IN28 OSDS28 IN27 OSDS27 IN26 OSDS26 IN25 OSDS25 IN24 OSDS24 IN23 OSDS23 IN22 OSDS22 IN21 OSDS21 IN20 OSDS20 IN19 OSDS19 IN18 OSDS18 IN17 OSDS17 IN16 OSDS16 OSD15 OSD14 OSD13 OSD12 OSD11 VNEG OSD10 OSD09 OSD08 VPOS OUT15 VNEG OUT14 Description Input Number 28. Control Pin: OSD Select Number 28. Input Number 27. Control Pin: OSD Select Number 27. Input Number 26. Control Pin: OSD Select Number 26. Input Number 25. Control Pin: OSD Select Number 25. Input Number 24. Control Pin: OSD Select Number 24. Input Number 23. Control Pin: OSD Select Number 23. Input Number 22. Control Pin: OSD Select Number 22. Input Number 21. Control Pin: OSD Select Number 21. Input Number 20. Control Pin: OSD Select Number 20. Input Number 19. Control Pin: OSD Select Number 19. Input Number 18. Control Pin: OSD Select Number 18. Input Number 17. Control Pin: OSD Select Number 17. Input Number 16. Control Pin: OSD Select Number 16. OSD Input Number 15. OSD Input Number 14. OSD Input Number 13. OSD Input Number 12. OSD Input Number 11. Analog Negative Power Supply. OSD Input Number 10. OSD Input Number 9. OSD Input Number 8. Analog Positive Power Supply. Output Number 15. Analog Negative Power Supply. Output Number 14. Pin 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Mnemonic VPOS OUT13 VNEG OUT12 VPOS OUT11 VNEG OUT10 VPOS OUT09 VNEG OUT08 VPOS OUT07 VNEG OUT06 VPOS OUT05 VNEG OUT04 VPOS OUT03 VNEG OUT02 VPOS OUT01 VNEG OUT00 VPOS OSD07 OSD06 OSD05 OSD04 OSD03 OSD02 OSD01 DGND Exposed Pad Description Analog Positive Power Supply. Output Number 13. Analog Negative Power Supply. Output Number 12. Analog Positive Power Supply. Output Number 11. Analog Negative Power Supply. Output Number 10. Analog Positive Power Supply. Output Number 9. Analog Negative Power Supply. Output Number 8. Analog Positive Power Supply. Output Number 7. Analog Negative Power Supply. Output Number 6. Analog Positive Power Supply. Output Number 5. Analog Negative Power Supply. Output Number 4. Analog Positive Power Supply. Output Number 3. Analog Negative Power Supply. Output Number 2. Analog Positive Power Supply. Output Number 1. Analog Negative Power Supply. Output Number 0. Analog Positive Power Supply. OSD Input Number 7. OSD Input Number 6. OSD Input Number 5. OSD Input Number 4. OSD Input Number 3. OSD Input Number 2. OSD Input Number 1. Digital Negative Power Supply. Connect to analog ground.
Rev. 0 | Page 10 of 36
ADV3200/ADV3201
TRUTH TABLE AND LOGIC DIAGRAM
Table 8. Operation Truth Table
CS X1 0 UPDATE X 1 CLK X DATA IN X Datai 2 DATA OUT X Datai-193 RESET 0 1 Operation/Comment Asynchronous reset. All outputs are disabled. The 193-bit shift register is reset to all 0s. The data on the serial DATA IN line is loaded into the serial register. The first bit clocked into the serial register appears at DATA OUT 193 clock cycles later. Switch matrix update. Data in the 193-bit shift register is transferred into the parallel latches that control the switch array and sync-tip clamps. Chip is not selected. No change in logic.
0
0
X
X
X
1
1
1 2
X
X
X
X
1
X = don't care. Datai: serial data.
DATA IN RESET CLK CS UPDATE
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
DATA OUT
CLR CLK
CLR CLK
CLR CLK
CLR CLK
CLR CLK
CLR CLK
CLR CLK
...
CLR CLK
CLR CLK
CLR CLK
CLR CLK
CLR CLK
CLR CLK
CLR CLK
CLR CLK
LE D LE D LE D LE D LE D LE D LE D OUT00 OUT00 OUT00 OUT00 OUT00 OUT00 OUT01 0 1 2 3 4 EN 0 LSB LSB LSB LSB LSB MSB LSB 192 191 190 189 188 187 186 CLR Q CLR Q CLR Q CLR Q CLR Q CLR Q CLR Q RESET
...
LE D OUT30 EN MSB 7 CLR Q
LE D OUT31 0 LSB 6 CLR Q
LE D OUT31 1 LSB 5 CLR Q
LE D OUT31 2 LSB 4 CLR Q
LE D OUT31 3 LSB 3 CLR Q
LE D OUT31 4 LSB 2 CLR Q
LE D OUT31 EN MSB 1 CLR Q
LE D OUT31 SYNC TIP EN 0 CLR Q
DECODE 1024 SWITCH MATRIX
07176-053
32
OUTPUT ENABLE
Figure 6. Logic Diagram
Rev. 0 | Page 11 of 36
ADV3200/ADV3201 I/O SCHEMATICS
OUT 4k (ADV3201 ONLY)
07176-054
CLK, UPDATE, DATA IN, OSDS, CS
1k 25k (CS ONLY) DGND
VREF
Figure 7. Enabled Output (See Also Figure 16)
Figure 12. Logic Input (See Also Figure 16)
DVCC
OUT 3.7pF
07176-055
4k (ADV3201 ONLY)
DATA OUT
VREF
DGND
Figure 8. Disabled Output (See Also Figure 16)
Figure 13. Logic Output (See Also Figure 16)
VREF
IN
VCLAMP
07176-056
6k 50A VNEG
07176-060
VNEG
Figure 9. Receiver (See Also Figure 16)
Figure 14. VCLAMP Input (See Also Figure 16)
VPOS 2.5k (5k FOR ADV3201) VREF
07176-058
VPOS
IN 5A VNEG
VNEG
Figure 10. Receiver with Sync-Tip Clamp Enabled (See Also Figure 16)
VPOS
DVCC 25k RESET
Figure 15. VREF Input (See Also Figure 16)
DVCC
07176-062
2.5k (5k FOR ADV3201)
07176-061
07176-059
DGND
1k
07176-057
VREF, VCLAMP, OSD, IN, OUT
CLK, RESET, UPDATE, CS, DATA IN, DATA OUT, OSDS
07176-063
DGND
VNEG
DGND
Figure 11. Reset Input (See Also Figure 16)
Figure 16. ESD Protection Map
Rev. 0 | Page 12 of 36
ADV3200/ADV3201 TYPICAL PERFORMANCE CHARACTERISTICS
ADV3200
VS = 2.5 V at TA = 25C, RL = 150 .
2 0 -2 OSDxx INxx
1 10pF 0 0pF -1 5pF 2pF 2
GAIN (dB)
-4 -6 -8 -10 -12
GAIN (dB)
-2
-3
07176-005
1
10 100 FREQUENCY (MHz)
1k
1
10 100 FREQUENCY (MHz)
1k
Figure 17. ADV3200 Small Signal Frequency Response, 200 mV p-p
Figure 20. ADV3200 Large Signal Frequency Response with Capacitive Loads, 2 V p-p
4 2 10pF 0 5pF 2pF
2 0 -2
GAIN (dB)
GAIN (dB)
-4 -6 OSDxx -8 -10 -12 INxx
-2 -4 -6 -8
0pF
07176-009
1
10 100 FREQUENCY (MHz)
1k
1
10 100 FREQUENCY (MHz)
1k
Figure 18. ADV3200 Large Signal Frequency Response, 2 V p-p
Figure 21. ADV3200 OSD Small Signal Frequency Response with Capacitive Loads, 200 mV p-p
2
4 10pF 2 0 0pF 5pF 2pF
1 10pF 5pF 2pF 0pF
0 GAIN (dB)
GAIN (dB)
-2 -4 -6 -8
-1
-2
-3
07176-010
1
10 100 FREQUENCY (MHz)
1k
1
10 100 FREQUENCY (MHz)
1k
Figure 19. ADV3200 Small Signal Frequency Response with Capacitive Loads, 200 mV p-p
Figure 22. ADV3200 OSD Large Signal Frequency Response with Capacitive Loads, 2 V p-p
Rev. 0 | Page 13 of 36
07176-013
-10
-4
07176-011
-10
07176-012
-4
ADV3200/ADV3201
600 90 80 500 70
NOISE (nV/ Hz)
07176-083
400
COUNT
60 50 40 30 20
300
200
100 10 362 370 378 FREQUENCY (MHz) 386 394
07176-079 07176-018
07176-085
0 354
0 0.001
0.01
0.1 FREQUENCY (MHz)
1
10
Figure 23. ADV3200 -3 dB Bandwidth Histogram, One Device, All 1024 Channels
500 475 450
NOISE (nV/ Hz) 140 120 100 80 60 40 20 0 0.001
Figure 26. ADV3200 Output Noise
-3dB BANDWIDTH (MHz)
425 400 375 350 325
07176-015
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
300
0.01
NUMBER OF ENABLED CHANNELS
0.1 FREQUENCY (MHz)
1
10
Figure 24. ADV3200 Small Signal Bandwidth vs. Enabled Channels
Figure 27. ADV3200 OSD Output Noise
0 -10 -20 VNEG -30
PSR (dB)
0 -10 -20 -30
CROSSTALK (dB)
100
07176-064
VPOS
-40 -50 -60 -70 -80
-40 -50 -60 -70 -80 0.1
-90
1
10 FREQUENCY (MHz)
-100
1
10 100 FREQUENCY (MHz)
1k
Figure 25. ADV3200 Power Supply Rejection
Figure 28. ADV3200 Crosstalk, One Adjacent Channel, RTO
Rev. 0 | Page 14 of 36
ADV3200/ADV3201
0 -10 -20 -30
1M
100k
CROSSTALK (dB)
-40 -50 -60 -70 -80 -90
07176-017
IMPEDANCE ()
10k
1k
100
10
1
10 100 FREQUENCY (MHz)
1k
1
10 FREQUENCY (MHz)
100
1k
Figure 29. ADV3200 Crosstalk, All Hostile, RTO
Figure 32. ADV3200 Output Impedance, Disabled
0 -10 -20
100
FEEDTHROUGH (dB)
-30 -40 -50 -60 -70 -80 -90
07176-019
IMPEDANCE ()
10
1
10M 100M FREQUENCY (Hz)
1G
2
10 100 FREQUENCY (MHz)
1k
Figure 30. ADV3200 Off Isolation, RTO
Figure 33. ADV3200 Output Impedance, Enabled
1M
0.12
100k
0.08
IMPEDANCE ()
10k
VOUT (V)
0.04
1k
0
100
-0.04 OSDxx
10
-0.08 INxx
07176-020
1
10 FREQUENCY (MHz)
100
1k
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
Figure 31. ADV3200 Input Impedance
Figure 34. ADV3200 Small Signal Pulse Response, 200 mV p-p
Rev. 0 | Page 15 of 36
07176-023
1 0.1
-0.12
07176-080
-100 1M
0.1
07176-021
-100
1 0.1
ADV3200/ADV3201
1.2 600
0.8
400 RISING EDGE
0.4
200
0
dV/dT (V/s)
VOUT (V)
0
-0.4 INxx -0.8 OSDxx
-200
FALLING EDGE
-400
07176-024
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
Figure 35. ADV3200 Large Signal Pulse Response, 2 V p-p
Figure 38. ADV3200 Slew Rate
2 UPDATE VOUT RISING EDGE
3.5
0.1
1
2.5
0
UPDATE (V)
VOUT (V)
0
VOUT (V)
1.5
-0.1
-1
VOUT FALLING EDGE
0.5
-0.2
07176-065
0
20
40 TIME (ns)
60
80
0
20
40 TIME (ns)
60
80
100
Figure 36. ADV3200 Switching Time
Figure 39. ADV3200 Switching Glitch
2 OSDS VOUT RISING EDGE
3
15
1
2
10
0
VOUT (mV)
OSDS (V)
VOUT (V)
1
5
-1 VOUT FALLING EDGE
0
0
07176-066
0
20
40 TIME (ns)
60
80
0
20
40 TIME (ns)
60
80
100
Figure 37. ADV3200 OSD Switching Time
Figure 40. ADV3200 OSD Switching Glitch
Rev. 0 | Page 16 of 36
07176-068
-2
-1 100
-5
07176-067
-2
-0.5 100
-0.3
07176-025
-1.2
-600
ADV3200/ADV3201
0.05 0.04 0.03
0.04 0.02
DIFFERENTIAL PHASE (Degrees)
07176-087
DIFFERENTIAL GAIN (%)
0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0.7 -0.5 -0.3 -0.1 0.1 0.3 INPUT DC OFFSET (V) 0.5 0.7
0 -0.02 -0.04 -0.06 -0.08 -0.10 -0.7
-0.5
-0.3
-0.1 0.1 0.3 INPUT DC OFFSET (V)
0.5
0.7
Figure 41. ADV3200 Differential Gain, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p
0.010
Figure 44. ADV3200 OSD Differential Phase, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p
280 260 IPOS, INEG (BROADCAST)
DIFFERENTIAL PHASE (Degrees)
0.005
240
IPOS, INEG (mA)
0
220 200 180 160 140 IPOS, INEG (ALL OUTPUTS DISABLED)
-0.005
-0.010
-0.015
120
07176-088
-0.5
-0.3
-0.1 0.1 0.3 INPUT DC OFFSET (V)
0.5
0.7
-30
-10
10 30 50 TEMPERATURE (C)
70
90
Figure 42. ADV3200 Differential Phase, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p
0.05 0.03 0.01
300 275 250
Figure 45. ADV3200 Supply Current vs. Temperature
DIFFERENTIAL GAIN (%)
-0.01 -0.03 -0.05 -0.07 -0.09
IPOS, INEG (mA)
225 200 175 150
-0.11 -0.13
07176-089
125
07176-026
-0.15 -0.7
-0.5
-0.3
-0.1 0.1 0.3 INPUT DC OFFSET (V)
0.5
0.7
100
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 NUMBER OF ENABLED OUTPUTS
Figure 43. ADV3200 OSD Differential Gain, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p
Figure 46. ADV3200 Supply Current vs. Enabled Outputs
Rev. 0 | Page 17 of 36
07176-098
-0.020 -0.7
100 -50
07176-090
ADV3200/ADV3201
250
180 160
200
140 120
150
COUNT
COUNT
07176-092
100 80 60
100
50
40 20
-1.5 -1.4 -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20
0
0
OFFSET (mV)
GAIN ERROR (%)
Figure 47. ADV3200 Input Offset Distribution, One Device, All 1024 Channels
Figure 50. ADV3200 Gain Error Distribution, One Device, All 1024 Channels
1.5 VOUT RISING EDGE 1.0 UPDATE
4
0.15
2pF 10pF
5pF
3
0.10 0pF
0.5
VOUT (V)
2
UPDATE (V)
VOUT (V)
0.05
0
1
0
-0.5
0
-0.05
-1.0 VOUT FALLING EDGE
-1
-0.10
07176-069
0
20
40 TIME (ns)
60
80
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
Figure 48. ADV3200 Enable Time
Figure 51. ADV3200 Small Signal Pulse with Capacitive Loads, 200 mV p-p
70 60 50 VOUT 40 30 20 10 0 -5 (VOUT - VIN)/VIN VIN
1.4 1.0 0.6 0.2 -0.2 -0.6 -1.0 -1.4
0.15 10pF
0.10
OUTPUT ERROR (%)
0.05 2pF
VOUT (V)
VOUT (V)
5pF 0pF
0
-0.05
-0.10
07176-070
0
5 TIME (ns)
10
15
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
Figure 49. ADV3200 Settling Time
Figure 52. ADV3200 OSD Small Signal Pulse with Capacitive Loads, 200 mV p-p
Rev. 0 | Page 18 of 36
07176-028
-0.15
07176-027
-1.5
-2 100
-0.15
07176-100
ADV3200/ADV3201
1.5 10pF 2pF 0pF
VOLTAGE (V) 2
5pF
1
VIN = 1.65V
VIN = 1.45V
1.0
0.5
VOUT (V)
0
0
VOUT @ VIN = 1.65V VOUT @ VIN = 1.45V
-0.5
-1
-1.0
07176-029
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
0
50
100 TIME (ns)
150
200
Figure 53. ADV3200 Large Signal Pulse with Capacitive Loads, 2 V p-p
Figure 55. ADV3200 Overdrive Recovery
1.5 10pF 2pF 0pF 5pF
1.0
0.5
VOUT (V)
0
-0.5
-1.0
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
Figure 54. ADV3200 OSD Large Signal Pulse with Capacitive Loads, 2 V p-p
07176-030
-1.5
Rev. 0 | Page 19 of 36
07176-077
-1.5
-2
ADV3200/ADV3201
ADV3201
VS = 3.3 V at TA = 25C, RL = 150 .
8 6 4 INxx
8
7
10pF 5pF 2pF 0pF
6 GAIN (dB)
GAIN (dB)
2 OSDxx 0 -2 -4 -6
5
4
3
07176-031
1
10 100 FREQUENCY (MHz)
1k
1
10 100 FREQUENCY (MHz)
1k
Figure 56. ADV3201 Small Signal Frequency Response, 200 mV p-p
Figure 59. ADV3201 Large Signal Frequency Response with Capacitive Loads, 2 V p-p
12 10
8 6 OSDxx 4 INxx
8 10pF
GAIN (dB)
GAIN (dB)
2 0 -2 -4 -6
6 4 2 0 -2 0pF
5pF 2pF
07176-032
1
10 100 FREQUENCY (MHz)
1k
1
10 100 FREQUENCY (MHz)
1k
Figure 57. ADV3201 Large Signal Frequency Response, 2 V p-p
Figure 60. ADV3201 OSD Small Signal Frequency Response with Capacitive Loads, 200 mV p-p
8
12 10 8 10pF 5pF 2pF
7 10pF 6 GAIN (dB) 5pF
GAIN (dB)
6 4 2 0 -2
0pF
5 2pF 4 0pF 3
07176-033
1
10 100 FREQUENCY (MHz)
1k
1
10 100 FREQUENCY (MHz)
1k
Figure 58. ADV3201 Small Signal Frequency Response with Capacitive Loads, 200 mV p-p
Figure 61. ADV3201 OSD Large Signal Frequency Response with Capacitive Loads, 2 V p-p
Rev. 0 | Page 20 of 36
07176-036
2
07176-034
07176-035
2
ADV3200/ADV3201
350 300 250
NOISE (nV/ Hz)
07176-037
160 140 120 100 80 60 40 20
07176-081 07176-041 07176-086
COUNT
200 150 100 50 0 308
312
316
320 324 328 332 FREQUENCY (MHz)
336
340
344
0 0.001
0.01
0.1 FREQUENCY (MHz)
1
10
Figure 62. ADV3201 -3 dB Bandwidth Histogram, One Device, All 1024 Channels
350 220 200 340
-3dB BANDWIDTH (MHz)
Figure 65. ADV3201 Output Noise
180 160
330
NOISE (nV/ Hz)
07176-038
140 120 100 80 60
320
310
40 20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
300
0 0.001
0.01
NUMBER OF ENABLED CHANNELS
0.1 FREQUENCY (MHz)
1
10
Figure 63. ADV3201 Small Signal Bandwidth vs. Enabled Channels
Figure 66. ADV3201 OSD Output Noise
10 0 -10 -20
PSR (dB) CROSSTALK (dB)
07176-084
0
-20
-40
-30 -40 -50 -60 -70 0.1
VPOS VNEG
-60
-80
-100
1
10 FREQUENCY (MHz)
100
-120
1
10 100 FREQUENCY (MHz)
1k
Figure 64. ADV3201 Power Supply Rejection
Figure 67. ADV3201 Crosstalk, One Adjacent Channel, RTO
Rev. 0 | Page 21 of 36
ADV3200/ADV3201
0 10k -20 1k
CROSSTALK (dB) IMPEDANCE ()
07176-040
-40
-60
100
-80
10 -100
1
10 100 FREQUENCY (MHz)
1k
1
10 FREQUENCY (MHz)
100
1k
Figure 68. ADV3201 Crosstalk, All Hostile, RTO
Figure 71. ADV3201 Output Impedance, Disabled
0
100
-20
FEEDTHROUGH (dB)
-60
-80
IMPEDANCE ()
-40
10
1
-100
07176-042
10M 100M FREQUENCY (Hz)
1G
2
10 100 FREQUENCY (MHz)
1k
Figure 69. ADV3201 Off Isolation, RTO
Figure 72. ADV3201 Output Impedance, Enabled
1M
0.12
100k
0.08
IMPEDANCE ()
10k
VOUT (V)
0.04
1k
0
100
-0.04 OSDxx
10
-0.08 INxx
07176-104 07176-045
1 0.1
1
10 FREQUENCY (MHz)
100
1k
-0.12
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
Figure 70. ADV3201 Input Impedance
Figure 73. ADV3201 Small Signal Pulse Response, 200 mV p-p
Rev. 0 | Page 22 of 36
07176-082
-120 1M
0.1
07176-043
-120
1 0.1
ADV3200/ADV3201
1.2 600
0.8
400 RISING EDGE
0.4
dV/dT (V/s) VOUT (V)
200
0
0
-0.4 OSDxx INxx
-200 FALLING EDGE
-0.8
-400
07176-046
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
Figure 74. ADV3201 Large Signal Pulse Response, 2 V p-p
Figure 77. ADV3201 Slew Rate
2 UPDATE 1 VOUT RISING EDGE
3.5
0.2
0 2.5
UPDATE (V)
VOUT (V)
0
1.5
VOUT (V)
-0.2
-0.4
VOUT FALLING EDGE -1 0.5 -0.6
07176-071
0
20
40 TIME (ns)
60
80
0
20
40 TIME (ns)
60
80
100
Figure 75. ADV3201 Switching Time
Figure 78. ADV3201 Switching Glitch
2 OSDS VOUT RISING EDGE
3
20 15 10
1
2 5
VOUT (mV) OSDS (V)
VOUT (V)
0 -5 -10 -15 -20 -25
0
1
-1 VOUT FALLING EDGE
0
07176-073
0
20
40 TIME (ns)
60
80
0
20
40 TIME (ns)
60
80
100
Figure 76. ADV3201 OSD Switching Time
Figure 79. ADV3201 OSD Switching Glitch
Rev. 0 | Page 23 of 36
07176-074
-2
-1 100
-30
07176-072
-2
-0.5 100
-0.8
07176-047
-1.2
-600
ADV3200/ADV3201
0.10 0.10 0.05 0.05
DIFFERENTIAL GAIN (%) DIFFERENTIAL PHASE (Degrees)
0 -0.05 -0.10 -0.15 -0.20 -0.25
0
-0.05
-0.10
07176-094
-0.5
-0.3
-0.1 0.1 0.3 INPUT DC OFFSET (V)
0.5
0.7
-0.5
-0.3
-0.1 0.1 0.3 INPUT DC OFFSET (V)
0.5
0.7
Figure 80. ADV3201 Differential Gain, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p
0.05 0.04
DIFFERENTIAL PHASE (Degrees)
Figure 83. ADV3201 OSD Differential Phase, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p
300 280 260 240 220 200 180 160 140 IPOS, INEG (BROADCAST)
0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04
07176-095
IPOS, INEG (mA)
IPOS, INEG (ALL OUTPUTS DISABLED)
-0.5
-0.3
-0.1 0.1 0.3 INPUT DC OFFSET (V)
0.5
0.7
-30
-10
10 30 50 TEMPERATURE (C)
70
90
Figure 81. ADV3201 Differential Phase, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p
0.1
300 275 250
Figure 84. ADV3201 Supply Current vs. Temperature
0
DIFFERENTIAL GAIN (%)
IPOS, INEG (mA)
-0.1
225 200 175 150
-0.2
-0.3
-0.4
125
07176-096
07176-048
-0.5 -0.7
-0.5
-0.3
-0.1 0.1 0.3 INPUT DC OFFSET (V)
0.5
0.7
100
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 NUMBER OF ENABLED OUTPUTS
Figure 82. ADV3201 OSD Differential Gain, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p
Figure 85. ADV3201 Supply Current vs. Enabled Outputs
Rev. 0 | Page 24 of 36
07176-091
-0.05 -0.7
120 -50
07176-097
-0.15 -0.7
-0.30 -0.7
ADV3200/ADV3201
350 300 250 200 150 100 50 0 140 120 100 80 60 40 20 0
COUNT
07176-093
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20
COUNT
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
GAIN ERROR (%) 2pF 5pF 0pF 4 6 8 10 12 TIME (ns) 14 16 18 5pF 10pF 0pF 4 6 8 10 12 TIME (ns) 14 16 18
-1.0 -0.9
-0.8 -0.7
OFFSET (mV)
Figure 86. ADV3201 Input Offset Distribution, One Device, All 1024 Channels
Figure 89. ADV3201 Gain Error Distribution, One Device, All 1024 Channels
1.5 UPDATE VOUT RISING EDGE
4
0.15
10pF
1.0
3
0.10
0.5
2
0.05
UPDATE (V)
VOUT (V)
VOUT (V)
0
1
0
-0.5
0
-0.05
-1.0 VOUT FALLING EDGE
-1
-0.10
07176-075
0
20
40 TIME (ns)
60
80
0
2
20
Figure 87. ADV3201 Enable Time
Figure 90. ADV3201 Small Signal Pulse with Capacitive Loads, 200 mV p-p
70 60 50 VOUT 40 30 20 10 0 -5 (VOUT - VIN)/VIN VIN
1.4 1.0 0.6 0.2 -0.2 -0.6 -1.0 -1.4
0.15
0.10
2pF
OUTPUT ERROR (%)
0.05
VOUT (V)
VOUT (V)
0
-0.05
-0.10
07176-076
0
5 TIME (ns)
10
15
0
2
20
Figure 88. ADV3201 Settling Time
Figure 91. ADV3201 OSD Small Signal Pulse with Capacitive Loads, 200 mV p-p
Rev. 0 | Page 25 of 36
07176-051
-0.15
07176-049
-1.5
-2 100
-0.15
07176-099
ADV3200/ADV3201
1.5 10pF 2pF 0.5 0pF 1 5pF 2 3 VIN = 2.3V VIN = 2.1V
1.0
VOLTAGE (V)
VOUT (V)
VOUT @ VIN = 2.3V 0 VOUT @ VIN = 2.1V -1
0
-0.5
-1.0
-2
07176-050
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
0
50
100 TIME (ns)
150
200
Figure 92. ADV3201 Large Signal Pulse with Capacitive Loads, 2 V p-p
Figure 94. ADV3201 Overdrive Recovery
1.5 10pF 1.0 2pF
5pF
0pF 0.5
VOUT (V)
0
-0.5
-1.0
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
Figure 93. ADV3201 OSD Large Signal Pulse with Capacitive Loads, 2 V p-p
07176-052
-1.5
Rev. 0 | Page 26 of 36
07176-078
-1.5
-3
ADV3200/ADV3201 THEORY OF OPERATION
The ADV3200/ADV3201 are single-ended crosspoint arrays with 32 outputs, each of which can be connected to any one of 32 inputs. Thirty-two switchable input stages are connected to each output buffer to form 32-to-1 multiplexers. There are 32 of these multiplexers, each with its inputs wired in parallel, for a total array of 1024 stages forming a multicast-capable crosspoint switch (see Figure 97). In addition to connecting to any of the nominal inputs (INxx), each output can also be connected to an associated OSDxx input through an additional 2-to-1 multiplexer at each output. This 2-to-1 multiplexer switches between the output of the 32-to-1 multiplexer and the OSDxx input.
FROM INPUT STAGES VPOS OSDS00
In the ADV3201, an internal resistive feedback network and reference buffer provide for a total output stage gain of +2 (see Figure 96). The input voltage to the reference buffer is the VREF pin. This voltage is common to the entire chip and needs to be driven from a low impedance source to avoid crosstalk.
VPOS FROM INPUT STAGES VNEG VPOS OSD00 2k OSDS00 x1 OUT00
VNEG
VPOS
x1 VNEG VPOS OUT00
2k
VREF
07176-007
VNEG
OSD00
07176-006
Figure 96. Conceptual Diagram of Single Output Channel, G = +2 (ADV3201)
VNEG
Figure 95. Conceptual Diagram of Single Output Channel, G = +1 (ADV3200)
Decoding logic for each output selects one (or none) of the input stages to drive the output stage. The enabled input stage drives the output stage, which is configured as a unity-gain amplifier in the ADV3200 (see Figure 95).
Each input to the ADV3200/ADV3201 is buffered by a receiver. This receiver provides overvoltage protection for the input stages by limiting signal swing. In the ADV3200, the output of the receiver is limited to 1.2 V about VREF, whereas in the ADV3201, the signal swing is limited to 1.2 V about midsupply. This receiver is configured as a voltage feedback unity-gain amplifier. Excess loop gain bandwidth product reduces the effect of the closed-loop gain on the bandwidth of the device.
BYPASS SYNC-TIP CLAMP OPTIONAL AC COUPLING CAPACITOR 75 GND
ADV3200/ADV3201
INxx
SYNC-TIP CLAMP
RECEIVER
SWITCH MATRIX
OUTPUT BUFFER G = +1 (ADV3200) G = +2 (ADV3201)
OUTxx
75 75 GND
VCLAMP
OSDxx
OSDSxx
VREF
Figure 97. ADV3200/ADV3201 Signal Chain (Single I/O Path)
Rev. 0 | Page 27 of 36
07176-110
ADV3200/ADV3201
In addition to a receiver, each input also has a sync-tip clamp for use in ac-coupled applications. All clamps are enabled or disabled according to the first serial data bit shifted in during programming logic. When enabled, the clamp forces the lowest input voltage to the voltage on the VCLAMP pin. The VCLAMP pin is common to the entire chip and needs to be driven from a low impedance source to avoid crosstalk.
VPOS VCLAMP VPOS
Care must be taken to reduce output capacitance, which results in more overshoot and frequency domain peaking. In addition, when the outputs are disabled and driven externally, the voltage applied to them must not exceed the valid output swing range for the ADV3200/ADV3201 in order to keep these internal amplifiers in their linear range of operation. Applying excess voltage to the disabled outputs can cause damage to the ADV3200/ADV3201 and should be avoided (see the Absolute Maximum Ratings section for guidelines). The internal connection of the ADV3200/ADV3201 is controlled by a serial logic interface. Serial loading into a first rank of latches preprograms each output. A global update signal (UPDATE) moves the programming data into the second rank of latches, simultaneously updating all outputs. A serial output pin (DATA OUT) allows devices to be daisy chained for singlepin programming of multiple ICs. A reset pin is available to avoid bus conflicts by disabling all outputs. This reset clears both the first and second rank of latches. The ADV3200 can operate on a single 5 V supply, powering both the signal path (with the VPOS/VNEG supply pins) and the control logic interface (with the DVCC/DGND supply pins). However, in order to easily interface to ground referenced video signals, split supply operation is possible with 2.5 V. (The ADV3201 is intended to operate on 3.3 V.) In the case of split supplies, a flexible logic interface allows the control logic supplies (DVCC/DGND) to be run off 3.3 V/0 V to 5 V/0 V while the core remains on split supplies.
VNEG IN00 OFF-CHIP CAPACITOR 5A
TO INPUT RECEIVER
07176-008
Figure 98. Conceptual Diagram of Sync-Tip Clamp in an AC-Coupled Application
The output stage of the ADV3200/ADV3201 is designed for low differential gain and phase error when driving composite video signals. It also provides slew current for fast pulse response when driving component video signals. The outputs of the ADV3200/ADV3201 can be disabled to minimize on-chip power dissipation. When disabled, a series of internal amplifiers drives internal nodes such that a wideband high impedance is presented at the disabled output, even when the output bus is under large signal swings. (In the ADV3201, there is 4 k of resistance terminated to the VREF voltage by the reference buffer.) This high impedance allows multiple ICs to be bussed together without additional buffering.
Rev. 0 | Page 28 of 36
ADV3200/ADV3201 APPLICATIONS INFORMATION
PROGRAMMING
The ADV3200/ADV3201 are programmed serially through a 193-bit serial word that updates the matrix and the state of the sync-tip clamps each time the part is programmed.
Reset
When powering up the ADV3200/ADV3201, it is usually desirable to have the outputs come up in the disabled state. The RESET pin, when taken low, causes all outputs to be disabled. After power-up, the UPDATE pin should be driven high prior to raising RESET. Because the data in the shift register is random after power-up, it should not be used to program the matrix, or the matrix can enter unknown states. To prevent this, do not apply a logic low signal to UPDATE initially after power-up. The shift register should first be loaded with the desired data, and then UPDATE can be taken low to program the device. The RESET pin has a 25 k pull-up resistor to DVCC that can be used to create a simple power-on reset circuit. A capacitor from RESET to ground holds RESET low for some time while the rest of the device stabilizes. The low condition causes all the outputs to be disabled. The capacitor then charges through the pull-up resistor to the high state, thus allowing the full programming capability of the device. The CS pin has a 25 k pull-down resistor to DGND.
Serial Programming Description
The serial programming mode uses the CLK, DATA IN, UPDATE, and CS device pins. The first step is to assert a low on CS to select the device for programming. The UPDATE signal should be high during the time that data is shifted into the serial port of the device. If UPDATE is low, the data is still shifted in, and the transparent, asynchronous latches allow the data to reach the matrix. This causes the matrix to try to update itself to every intermediate state defined by the shifted-in data. The data at DATA IN is clocked in at every rising edge of CLK. A total of 193 bits must be shifted in to complete the programming. For each of the 32 outputs, there are five bits (D4 to D0) that determine the source of its input followed by one bit (D5) that determines the enabled state of the output. If D5 is low (output disabled), the five associated bits (D4 to D0) do not matter because no input is switched to that output. The first bit shifted into the logic is used to enable or disable the sync-tip clamps. If this bit is low, the sync-tip clamps are disabled; otherwise, they are enabled. The sync-tip clamp bit is shifted in first, followed by the most significant output address data (OUT31). The enable bit (D5) is shifted in first, followed by the input address (D4 to D0) entered sequentially with D4 first and D0 last. Each remaining output is programmed sequentially, until the least significant output address data is shifted in. At this point, UPDATE can be taken low, which causes the device to be programmed according to the data that was just shifted in. The second-rank latches are asynchronous and, when UPDATE is low, they are transparent. If more than one ADV3200/ADV3201 device is to be serially programmed in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain. All of the CLK and UPDATE pins should be connected in parallel and operated as described previously. The serial data is input to the DATA IN pin of the first device of the chain, and it ripples through to the last. Therefore, the data for the last device in the chain should come at the beginning of the programming sequence. The length of the programming sequence is 193 bits multiplied by the number of devices in the chain.
AC COUPLING OF INPUTS
Using ac-coupled inputs presents a challenge for video systems operating from low supply voltages or from a single 5 V supply. In NTSC and PAL video systems, 700 mV is the approximate difference between the maximum signal voltage and the black level, assuming that sync has been stripped. However, as shown in Figure 99, a dynamic range of twice the maximum signal swing is required if the inputs are to be ac-coupled. A solution to this extended requirement for dynamic range is the sync-tip clamp feature.
WHITE LINE WITH BLACK PIXEL +700mV VREF BLACK LINE WITH WHITE PIXEL +5V VSIGNAL VINPUT = VREF + VSIGNAL VREF ~ VAVG VREF IS A DC VOLTAGE SET BY THE RESISTORS GND VREF VAVG VAVG
-700mV
Figure 99. Pathological Case for Input Dynamic Range
Rev. 0 | Page 29 of 36
07176-102
ADV3200/ADV3201
Sync-Tip Clamp for AC-Coupled Inputs
The ADV3200/ADV3201 sync-tip clamp, when enabled, clamps the most negative voltage of the video to equal VCLAMP. This provides the correct dc level to the crosspoint switch and ensures that, regardless of average picture level, the dynamic range requirement is only the maximum input signal swing. A basic method for ac coupling the input is to provide a series capacitor at the input of the ADV3200/ADV3201. If a termination is provided, locate it before the series coupling capacitor. Place the series coupling capacitor as close to the input pin as possible. It is important to choose the correct value for the ac coupling capacitor at the input to the ADV3200/ADV3201. Too small a value generates unacceptable droop as shown in Figure 100. Using a large enough value, such as a 100 nF ac coupling capacitor, prevents this droop, as shown in Figure 101. The sync-tip clamp is enabled or disabled by the sync-tip clamp enable bit in the 193-bit word used to serially program the ADV3200/ADV3201. The sync-tip clamp enable bit turns the clamp function on or off for all channels; there is no clamp on/off control for individual channels. The sync-tip clamp function works only with signals that contain sync-tips, such as composite video. Signals that do not have sync-tips appear distorted if they are run through the clamp function. The range of VCLAMP is -1 V to +0.3 V for the ADV3200 at 2.5 V operation, and -0.5 V to +0.3 V for the ADV3201 at 3.3 V operation. If driving VCLAMP externally, refer to Figure 14 for the input circuitry. Note that the VCLAMP pin has a 6 k resistor tied to an on-chip VREF buffered voltage and a 50 A current source that sets VCLAMP nominally to 300 mV below VREF. It is recommended that bypassing be added on the VCLAMP pin, because noise and offsets can be injected through this pin.
0.7 0.6 0.1 0.5 0.4
INPUT VIDEO (V)
0.2
0
VOUT (V)
0.3 0.2 0.1 0 -0.1 -0.2 VCLAMP 0 10 20 30 40 50 60 TIME (s) 70 80 90 100
07176-108 07176-109
-0.1
-0.2
VREF = 0V
-0.3
0
10
20
30
40
50 60 TIME (s)
70
80
90
100
Figure 100. Video Signal with a 1 nF AC Coupling Capacitor
0.2 0.5 0.4 0.1
OUTPUT VIDEO (V)
07176-106
-0.4
-0.3
Figure 102. Input Video Signal into Sync-Tip Clamp
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 VCLAMP = -0.5V
07176-107
VOUT (V)
0
VREF = 0V
-0.1
-0.2
-0.3
0
10
20
30
40
50 60 TIME (s)
70
80
90
100
-0.5
0
10
20
30
40
50 60 TIME (s)
70
80
90
100
Figure 101. Video Signal with a 100 nF AC Coupling Capacitor
Figure 103. AC-Coupled Video Through ADV3201, Sync-Tip Clamp Enabled
Rev. 0 | Page 30 of 36
ADV3200/ADV3201
ON-SCREEN DISPLAY (OSD)
The ADV3200/ADV3201 features dedicated 2:1 muxes for each of the 32 outputs that allow external video or dc levels to be inserted and switched in with the regular input channel. The OSD mux switches in 20 ns, allowing for information such as text or other picture-on-picture signals to be displayed. The OSDSxx pins are the control switches used to switch each corresponding OSD mux (high = OSD, low = regular input). Pulling OSDSxx high switches the signal that appears at the OSDxx input to the corresponding output. Setting OSDSxx low switches the signal at INxx to the corresponding output. This switching can be done on a pixel-by-pixel basis for each scan line, and in this way any video signal, including graphics, characters, or text, can be inserted to be displayed at the output. The OSD signal must be synchronized to the incoming video signal that it is switching between; therefore, the OSDS signal must be correctly timed in order to correctly place the OSD signal on the horizontal line. In addition, the OSDxx inputs do not have the sync-tip clamp feature described in the previous section, so the dc level must be set appropriately at the OSDxx input.
POWER DISSIPATION
Calculation of Power Dissipation
9 TJ = 150C 8
MAXIMUM POWER (W)
7
6
5
4
25
35 45 55 65 AMBIENT TEMPERATURE (C)
75
85
Figure 104. Maximum Die Power Dissipation vs. Ambient Temperature
The curve in Figure 104 is calculated from
PD , MAX = TJUNCTION , MAX - TAMBIENT JA
DECOUPLING
The signal path of the ADV3200/ADV3201 is based on high open-loop gain amplifiers with negative feedback. Dominantpole compensation is used on chip to stabilize these amplifiers over the range of expected applied swing and load conditions. To guarantee this designed stability, proper supply decoupling is necessary. Signal-generated currents must return to their sources through low impedance paths at all frequencies in which there is still loop gain (up to 300 MHz at a minimum). A wideband parallel capacitor arrangement is necessary to properly decouple the ADV3200/ADV3201. The VREF and VCLAMP pins should be considered reference pins, not power supply pins, because they are both inputs to on-chip buffers. Because the VREF pin is used as a ground reference in the ADV3200/ADV3201, care must be taken to produce a low noise VREF source over the entire range of frequencies of interest.
(1)
For example, if the ADV3200/ADV3201 is enclosed in an environment at 45C (TA), the total on-chip dissipation under all load and supply conditions must not be allowed to exceed 6.5 W. When calculating on-chip power dissipation, it is necessary to include the rms current being delivered to the load, multiplied by the rms voltage drop on the ADV3200/ADV3201 output devices. For a sinusoidal output, the on-chip power dissipation due to the load can be approximated by PD,OUTPUT = (VPOS - VOUTPUT,RMS) x IOUTPUT,RMS For a nonsinusoidal output, the power dissipation should be calculated by integrating the on-chip voltage drop multiplied by the load current over one period. The user can subtract the quiescent current for the Class AB output stage when calculating the loaded power dissipation. For each output stage driving a load, subtract the quiescent power according to PDQ,OUTPUT = (VPOS - VNEG) x IOUTPUT,QUIESCENT (3) where IOUTPUT,QUIESCENT = 0.95 mA for each single-ended output pin. For each disabled output, the quiescent power supply current in VPOS and VNEG drops by approximately 4 mA. (2)
Rev. 0 | Page 31 of 36
07176-003
3 15
ADV3200/ADV3201
VPOS IOUTPUT, QUIESCENT QNPN VOUTPUT
QPNP IOUTPUT IOUTPUT, QUIESCENT
07176-111
When there are many signals in close proximity in a system, as is undoubtedly the case in a system that uses the ADV3200/ ADV3201, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system that uses one or more crosspoint devices.
Types of Crosstalk
Crosstalk can be propagated by any of three means: electric field, magnetic field, and sharing of common impedances. This section explains these effects. Every conductor can be both a radiator of electric fields and a receiver of electric fields. The electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance (for example, free space), couples with the receiver, and induces a voltage. This voltage is an unwanted crosstalk signal in any channel that receives it. Currents flowing in conductors create magnetic fields that circulate around the currents. These magnetic fields then generate voltages in any other conductors whose paths they link. The undesired induced voltages in these other channels are crosstalk signals. The channels with crosstalk can be said to have a mutual inductance that couples signals from one channel to another. The power supplies, grounds, and other signal return paths of a multichannel system are generally shared by the various channels. When a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the common impedance. All these sources of crosstalk are vector quantities, so the magnitudes cannot simply be added together to obtain the total crosstalk. In fact, there are conditions where driving additional circuits in parallel in a given configuration can actually reduce the crosstalk.
VNEG
Figure 105. Simplified Output Stage
Example For the ADV3200, in an ambient temperature of 85C, with all 32 outputs driving 1 V rms into 150 loads and power supplies at 2.5 V, follow these steps: 1. Calculate the power dissipation of the ADV3200 using data sheet quiescent currents. Disregard VDD current, which is insignificant. PD,QUIESCENT = (VPOS x IVPOS) + (VNEG x IVNEG) PD,QUIESCENT = (2.5 V x 250 mA) + (2.5 V x 250 mA) = 1.25 W 2. Calculate the power dissipation from the loads. PD,OUTPUT = (VPOS - VOUTPUT,RMS) x IOUTPUT,RMS PD,OUTPUT = (2.5 V - 1 V) x (1 V/150 ) = 10 mW There are 32 outputs, therefore, 32 output currents. nPD,OUTPUT = 32 x 10 mW = 0.32 W 3. Subtract the quiescent output stage current for the number of loads (32 in this example). The output stage is either standing or driving a load, but the current needs to be counted only once (valid for output voltages > 0.5 V). PDQ,OUTPUT = (VPOS - VNEG) x IOUTPUT,QUIESCENT PDQ,OUTPUT = (2.5 V - (-2.5 V)) x (0.95 mA) = 4.75 mW There are 32 outputs, therefore, 32 output currents. nPDQ,OUTPUT = 32 x 4.75 mW = 0.15 W 4. Verify that the power dissipation does not exceed the maximum allowed value. PD,ON-CHIP = PD,QUIESCENT + nPD,OUTPUT - nPDQ,OUTPUT PD,ON-CHIP = 1.25 W + 0.32 W - 0.15 W= 1.42 W As shown in Figure 104 or Equation 1, this power dissipation is below the maximum allowed dissipation for all ambient temperatures up to and including 85C.
Areas of Crosstalk
A practical ADV3200/ADV3201 circuit must be mounted to some sort of circuit board in order to connect it to power supplies and measurement equipment. Great care has been taken to create an evaluation board that adds minimum crosstalk to the intrinsic device. This, however, raises the issue that the crosstalk of a system is the combination of the intrinsic crosstalk of the devices and the crosstalk of the circuit board to which the devices are mounted. It is important to separate these two areas when attempting to minimize the effect of crosstalk. In addition, crosstalk can occur among the inputs to a crosspoint switch and among the outputs. It can also occur from input to output. Techniques are discussed in the following sections for diagnosing which part of a system is contributing to crosstalk.
CROSSTALK
Many systems, such as broadcast video and KVM switches, that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing any of the others in the system. Crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel.
Rev. 0 | Page 32 of 36
ADV3200/ADV3201
Measuring Crosstalk
Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. The measurement is usually expressed as decibels below the magnitude of the test signal. The crosstalk is expressed by
A (s ) XT = 20 log 10 SEL A (s ) TEST
system channels are driven in parallel. In general, this yields the worst crosstalk number, but this is not always the case due to the vector nature of the crosstalk signal. Other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. These crosstalk measurements are generally higher than those of more distant channels; therefore, they can serve as a worstcase measure for any other one-channel or two-channel crosstalk measurements.
(4)
where: s = j (Laplace transform variable). ASEL(s) is the amplitude of the crosstalk induced signal in the selected channel. ATEST(s) is the amplitude of the test signal. It can be seen that crosstalk is a function of frequency but not a function of the magnitude of the test signal (to first order). In addition, the crosstalk signal has a phase relative to the test signal associated with it. A network analyzer is most commonly used to measure crosstalk over a frequency range of interest. It can provide both magnitude and phase information about the crosstalk signal. As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the 32 x 32 matrix of the ADV3200/ADV3201, note the number of crosstalk terms that can be considered for a single channel, for example, the IN00 input. IN00 is programmed to connect to one of the ADV3200/ ADV3201 outputs where the measurement can be made. First, the crosstalk terms associated with driving a test signal into each of the other 31 inputs can be measured one at a time, while applying no signal to IN00. Then the crosstalk terms associated with driving a parallel test signal into all 31 other inputs can be measured two at a time in all possible combinations, then three at a time, and so on until, finally, there is only one way to drive a test signal into all 31 other inputs in parallel. Each of these cases is legitimately different from the others and may yield a unique value, depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then specify them. In addition, this describes the crosstalk matrix for just one input channel. A similar crosstalk matrix can be proposed for every other input. In addition, if the possible combinations and permutations for connecting inputs to the other outputs (not used for measurement) are taken into consideration, the numbers quickly grow to astronomical proportions. If a larger crosspoint array of multiple ADV3200/ADV3201 devices is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected as a guide for a practical measurement of crosstalk. One common method is to measure all hostile crosstalk; this means that the crosstalk to the selected channel is measured while all other
Input and Output Crosstalk
Capacitive coupling is voltage-driven (dV/dt) but is generally a constant ratio. Capacitive crosstalk is proportional to input or output voltage, but this ratio is not reduced by simply reducing signal swings. Attenuation factors must be changed by changing impedances (lowering mutual capacitance), or destructive canceling must be utilized by summing equal and out of phase components. For high input impedance devices such as the ADV3200/ADV3201, capacitances generally dominate inputgenerated crosstalk. Inductive coupling is proportional to current (dI/dt) and often scales as a constant ratio with signal voltage, but it also shows a dependence on impedances (load current). Inductive coupling can also be reduced by constructive canceling of equal and out of phase fields. In the case of driving low impedance video loads, output inductances contribute highly to output crosstalk. The flexible programming capability of the ADV3200/ADV3201 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. Some examples are illustrative. A given input pair (IN07 in the middle for this example) can be programmed to drive OUT07 (also in the middle). The inputs to IN07 are terminated to ground (via 50 or 75 resistors) and no signal is applied. All the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except OUT07 disabled. Because the grounded IN07 input is programmed to drive OUT07, no signal should be present. Any signal that is present can be attributed to the other 15 hostile input signals because no other outputs are driven (they are all disabled). Thus, this method measures all the hostile input contribution to crosstalk into IN07. Of course, this method can be used for other input channels and combinations of hostile inputs. For output crosstalk measurement, a single input channel is driven (IN00, for example) and all outputs other than a given output (IN07 in the middle) are programmed to connect to IN00. OUT07 is programmed to connect to IN15 (far away from IN00), which is terminated to ground. Thus OUT07 should not have a signal present because it is listening to a quiet input. Any signal measured at OUT07 can be attributed to the output crosstalk of the other 15 hostile outputs. Again, this method can be modified to measure other channels and other crosspoint matrix combinations.
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ADV3200/ADV3201
Effect of Impedances on Crosstalk
Input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the impedance of the drive source, the lower the magnitude of the crosstalk. The dominant crosstalk mechanism on the input side is capacitive coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk. However, significant current can flow through the input termination resistors and the loops that drive them. Thus, the PCB on the input side can contribute to magnetically coupled crosstalk. From a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. For low frequencies, the magnitude of the crosstalk is given by
XT = 20 log 10 [(RS C M ) x s ]
must be carefully detailed are grounding, shielding, signal routing, and supply bypassing. The input and output signals have minimum crosstalk if they are located between ground planes on layers above and below and are separated by ground in between. Locate vias as close to the IC as possible to carry the inputs and outputs to the inner layer. The input and output signals surface at the input termination resistors and the output series back-termination resistors. To the extent possible, separate these signals as soon as they emerge from the IC package.
PCB TERMINATION LAYOUT
As frequencies of operation increase, proper routing of transmission line signals becomes more important. The bandwidth of the ADV3200/ADV3201 is large enough so that using high impedance routing does not provide a flat in-band frequency response for practical signal trace lengths. It is necessary for the user to choose a characteristic impedance suitable for the application and to properly terminate the input and output signals of the ADV3200/ADV3201. Traditionally, video applications use 75 single-ended environments. For flexibility, the ADV3200/ADV3201 does not contain onchip termination resistors. This flexibility in application comes with some board layout challenges. The distance between the termination of the input transmission line and the ADV3200/ ADV3201 die is a high impedance stub and causes reflections of the input signal. With some simplification, it can be shown that these reflections cause peaking of the input at regular intervals in frequency, dependent on the propagation speed (vP) of the signal in the chosen board material and the distance (d) between the termination resistor and the ADV3200/ADV3201. If the distance is great enough, these peaks can occur in band. In fact, practical experience shows that these peaks are not high-Q, and should be pushed out to three or four times the desired bandwidth in order to not have an effect on the signal. For a board designer using FR4 (vP = 144 x 106 m/s), this means that the ADV3200/ADV3201 input should be placed no farther than 2 cm after the termination resistors and, preferably, should be placed even closer. Therefore, 2 cm PCB routing equates to d = 2 x 10-2 m in the calculations.
(5)
where: RS is the source resistance. CM is the mutual capacitance between the test signal circuit and the selected circuit. s is the Laplace transform variable. From the preceding equation, it can be observed that this crosstalk mechanism has a high-pass nature; it can also be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. If the input is driven from a 75 terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. On the output side, the crosstalk can be reduced by driving a lighter load. Although the ADV3200/ADV3201 are specified with excellent differential gain and phase when driving a standard 150 video load, the crosstalk will be higher than the minimum obtainable due to the high output currents. These currents induce crosstalk via the mutual inductance of the output pins and bond wires of the ADV3200/ADV3201. From a circuit standpoint, the output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drives a load resistor. For low frequencies, the magnitude of the crosstalk is given by
s XT = 20 log 10 M XY x RL
(6)
f PEAK =
(2n + 1) x v P
4d
(7)
where: MXY is the mutual inductance of Output X to Output Y. RL is the load resistance on the measured output. s is the Laplace transform variable. This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing RL. The mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length.
where n = {0, 1, 2, 3, ...}. In some cases, it is difficult to place the termination close to the ADV3200/ADV3201 due to space constraints and large resistor footprints. A better solution in this case is to maintain a controlled transmission line past the ADV3200/ADV3201 inputs and to terminate the end of the line. This method is known as fly-by termination. The input impedance of the ADV3200/ADV3201 is large enough, and the stub length inside the package is small enough, that this works well in practice.
PCB Layout
Extreme care must be exercised to minimize additional crosstalk generated by system circuit boards. The areas that
Rev. 0 | Page 34 of 36
ADV3200/ADV3201
INxx
ADV3200/ ADV3201
OUTxx
transmission line is a stub that should be minimized in length and parasitics using the discussed guidelines. Although the examples discussed so far are for input termination, the theory is similar for output back termination. Taking the ADV3200/ADV3201 as an ideal voltage source, any distance of routing between the ADV3200/ADV3201 and a back-termination resistor is a stub that creates reflections. For this reason, place back-termination resistors close to the ADV3200/ADV3201. In practice, because back-termination resistors are series elements, their footprint in the routing is narrower, and it is easier to place them close to the ADV3200/ ADV3201 outputs in board layout.
Figure 106. Fly-By Input Termination (Grounds for the Two Transmission Lines Must Be Tied Together Close to the INxx Pin)
If multiple ADV3200/ADV3201s are to be driven in parallel, a fly-by input termination scheme is very useful, but the distance from each ADV3200/ADV3201 input to the driven input
USB DIGITAL CONTROL 6 CLK, DATA IN, DATA OUT, UPDATE, CS, RESET PADS FOR VCLAMP CAPS BNC 75 75 0402 IN[2:0], OSD[24:22], OSD[18:16]
FROM PC
VPOS VNEG DVCC DGND OUT[31], OUT[15:0] 75 TEST POINT OUT[15:0] 75
[CLK, DATA IN, DATA OUT, UPDATE, CS, RESET]
07176-103
75
OUT[18:16] 150
AD8003
464
75
BNC
ADV3200/ADV3201
RCA 75 75 0402 IN[5:3], OSD[21:19] OUT[21:19] 150 RCA 75 75 0402 OSD[27:25]
464
AD8003
464 464
75
RCA
SMA
50 50
0402
IN[8:6], OSD[30:28] OUT[24:22] 75 75 BNC
IN[31:9], OSD[31], OSD[15:0] 75
OUT[27:25]
75
75
RCA
75 OUT[30:28] VCLAMP OSDS[31:0] VREF TEST POINT 100nF 10nF 1nF TEST POINT 100nF 10nF
43 86.6
50
SMA
1nF
OSDS[18:16]
07176-101
OSDS[31:0] TO HIGH SPEED BREAKOUT
2k 1k
BNC
TEST POINT OSDS[24:22]
Figure 107. Evaluation Board Simplified Schematic
Rev. 0 | Page 35 of 36
ADV3200/ADV3201 OUTLINE DIMENSIONS
1.60 MAX
26.20 26.00 SQ 25.80
0.75 0.60 0.45
1.00 REF SEATING PLANE
24.10 24.00 SQ 23.90
133 132 133 132
21.50 REF
176 1
176 1 PIN 1
TOP VIEW
(PINS DOWN)
EXPOSED PAD
7.80 REF
1.45 1.40 1.35 0.15 0.10 0.05 0.08 COPLANARITY
0.20 0.15 0.09 7 3.5 0
BOTTOM VIEW
(PINS UP)
44 45 88 89 89 88 45 44
VIEW A
ROTATED 90 CCW
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD
Figure 108. 176-Lead Low Profile Quad Flat Package [LQFP_EP] (SW-176-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADV3200ASWZ 1 ADV3201ASWZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 176-Lead Low Profile Quad Flat Package [LQFP_EP] 176-Lead Low Profile Quad Flat Package [LQFP_EP]
Package Option SW-176-1 SW-176-1
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07176-0-10/08(0)
Rev. 0 | Page 36 of 36
081808-A
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

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